The continued delay in extreme ultra violet (EUV) lithography is driving the introduction of increasingly complex, costly and design-restrictive double-patterning (DP) solutions. As wiring pitches decrease (e.g., below 50 nanometer (nm) with 193 nm immersion), immersion lithography has involved the use of sidewall image transfer (SIT) double-patterning to overcome the overlay-induced dielectric breakdown failures that limit the achievable pitch scaling with older conventional litho-etch-litho-etch (LELE) double-patterning.
In SIT double-patterning, frequency doubling of the lithography-formed images does not occur by interdigitating two exposures (as in LELE), but by depositing sidewall spacers onto both sides of a lithographically-formed image. A second exposure, referred to as a “block” mask, is then used to add two-dimensional detail to the images formed by the SIT process.
However, a challenge in patterning approaches, e.g., SIT DP comes from the design rules necessary to ensure clean “block mask” generation. For example, line-ends of wire shapes in the layout (e.g., router-generated layout) are constrained such that the resulting block mask is free of minimum width space violations. Further, corner rounding effects on the block mask can cause unmanufacturable line-end angles.
These process constraints on the block mask result in line-end stagger rules, which can be described as:
For two line ends facing opposite directions, a line end stagger on neighboring tracks of, +K>Stagger>−K is forbidden; and
For line ends facing the same direction, a line end stagger on neighboring tracks of, +K>Stagger>0 as well as 0>Stagger>−K are forbidden.
However, implementing these line-end stagger rules in a conventional layout router will greatly reduce routing efficiency, and make the use of certain patterning approaches (e.g., SIT) unfeasible. This issue may be particularly significant for design rules that span multiple neighboring tracks, e.g., a line end stagger of +K>Stagger>−K is allowed if the offending line ends are separated by two empty tracks.
Further, in addition to the line-end stagger rules, the line ends must also satisfy two minimum spacing rules: 1) line-end to line-end spacing rule (T); and 2) line-end to line-side rule (E). These two rules come into play when line edges face one another with a non-minimum run length.
It is known in the art that line-end spacing rules cause challenges in conventional routers, primarily because it is difficult to model these rules precisely. Typically, T>E, and it is sometimes not known whether T or E applies prior to modeling. Stagger spacing rules can introduce several further complexities to the modeling of line-end spacings. For line-ends that occur in adjacent routing tracks, there are also several spacing choices relative to neighboring elements, for example: 0, −K, +K. The combination of spacing rules on the same (and adjacent) tracks, with discrete, non-continuous solutions, can have a negative impact on the efficiency and optimality of path search algorithms.